quando provo a simulare questo:
-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity rds2in is
port ( clk : in std_logic;
reset : in std_logic;
a : in std_logic;
b : in std_logic;
goal : out std_logic
);
end entity rds2in;

architecture RTL of rds2in is
--dichiarazione del component FFD
component FFD
port (CLK, D, reset : in STD_LOGIC;
Q : out STD_LOGIC);
end component;

signal D,Q :STD_LOGIC_VECTOR (3 downto 0);
signal x,z: STD_LOGIC;

begin

inst0: FFD port map (CLK=>CLK, D=>a, reset=>reset, Q=>Q(0) );
inst1: FFD port map (CLK=>CLK, D=>Q(0), reset=>reset, Q=>Q(1) );
inst2: FFD port map (CLK=>CLK, D=>Q(1), reset=>reset, Q=>Q(2) );
inst3: FFD port map (CLK=>CLK, D=>b, reset=>reset, Q=>Q(3) );
inst4: FFD port map (CLK=>CLK, D=>Q(3), reset=>reset, Q=>Q(4) );
inst5: FFD port map (CLK=>CLK, D=>Q(4), reset=>reset, Q=>Q(5) );
x <= ( not(Q(2)) and Q(1) ) and Q(3);
Z <= ( not(Q(3)) and Q(4) ) and Q(5);
goal <= x and z;

end architecture RTL;

--TEST BENCH--
library IEEE;
use IEEE.std_logic_1164.all;

entity rds2in_tb is
end rds2in_tb;

architecture behaviour of rds2in_tb is
component rds2in is
port ( clk : in std_logic;
reset : in std_logic;
a : in std_logic;
b : in std_logic;
goal : out std_logic
);
end component;

-- Clock period definitions
constant clk_period : time := 1 us;

signal CLK,a,b: STD_LOGIC := '0';
signal reset: STD_LOGIC :='1';
signal goal: STD_LOGIC;

signal I : integer := 0;
signal TEST_GOAL, errore: STD_LOGIC := '0';

begin
clk_process: process -- precesso di generazione del CLK a 1 Hz
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
I<=I+1;

if I=20 then wait;
else null;
end if;

end process;

UUT: rds2in port map (CLK => CLK, reset => reset, a=>a, b=>b, goal=>goal);

stim_proc: process
begin
reset<='1';
wait for clk_period*3;
reset<='0';a<='0'; b<='0';
wait for clk_period;
a<='0'; b<='1';
wait for clk_period;
a<='1'; b<='0';
wait for clk_period;
a<='1'; b<='1';
wait for clk_period;
a<='1'; b<='0';
wait for clk_period;
a<='0'; b<='1';
wait for clk_period;
a<='1'; b<='1';
wait for clk_period;
a<='1'; b<='1';
wait for clk_period;
a<='0'; b<='0';
wait for clk_period;
a<='1'; b<='0';
wait for clk_period;

wait;

end process;

test_goal_proc: process
begin
wait for clk_period/2;
test_goal<='0';
wait for clk_period*9;
test_goal<='1';
wait for clk_period;
test_goal<='0';
wait for clk_period;
wait;
end process;

ERRORE <= '0' when (goal=test_goal) else '1' after 1 ns;
assert (ERRORE='0')
report "attenzione!"
severity WARNING;

end behaviour;
---------------------------------------------------------------------------

mi dà questi errori:

/usr/lib/ghdl/libexec/gcc/i686-linux-gnu/4.3.4/ghdl1:*command-line*: cannot open RDS2in.vhdl
/usr/lib/ghdl/bin/ghdl: compilation error
error: cannot find entity or configuration ffd
/usr/lib/ghdl/bin/ghdl: compilation error
error: cannot find entity or configuration rds2in
/usr/lib/ghdl/bin/ghdl: compilation error
error: cannot find entity or configuration rds2in_tb
/usr/lib/ghdl/bin/ghdl: compilation error
/usr/lib/ghdl/bin/ghdl: file 'rds2in_tb' does not exists
/usr/lib/ghdl/bin/ghdl: Please elaborate your design.

GTKWave Analyzer v3.3.10 (w)1999-2010 BSI

Error opening .vcd file 'out.vcd'.
-----------------------------------------------------------------------------------

da tenere presente che qui ho omesso la descrizione del FFD(che ho fatto all'inizio)

e infine questo è il file con cui lancio la simulazione:

ghdl -a RDS2in.vhdl

ghdl -e FFD

ghdl -e rds2in

ghdl -e rds2in_tb

ghdl -r rds2in_tb --vcd=out.vcd

gtkwave out.vcd