library IEEE;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all; 


--=======================================================
--  ENTITY declarations
--=======================================================
entity top_level_examples_vhdl_qsys is
port ( 
      CLOCK_50      : in  std_logic;
	   KEY           : in  std_logic_vector(1 downto 0);
		SW            : in  std_logic_vector(3 downto 0);
	   LED           : out std_logic_vector(7 downto 0)
		);
end top_level_examples_vhdl_qsys;

	   
architecture struct of top_level_examples_vhdl_qsys is


COMPONENT pll IS
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
		);
END COMPONENT;

component  qsys_first_project is
	port (
		clk_clk              : in  std_logic                    := '0'; --           clk.clk
		reset_reset_n        : in  std_logic                    := '0'; --         reset.reset_n
		pio_operation_export : out std_logic_vector(7 downto 0)         -- pio_operation.export
	);
end component;

constant c_2MHz     : std_logic_vector(20 downto 0) := "111101000010001111111"; 
constant c_2MHz_2   : std_logic_vector(20 downto 0) := "011110100001000111111"; 
constant c_2MHz_4   : std_logic_vector(20 downto 0) := "001111010000100011111"; 
constant c_2MHz_8   : std_logic_vector(20 downto 0) := "001111010000100011111"; 
type t_state is (s_IDLE, s_START_COUNT);

signal state        : t_state;
signal counter      : std_logic_vector(20 downto 0);
signal user_clk     : std_logic;
signal i_led        : std_logic_vector(7 downto 0);
signal operation_reg: std_logic_vector(7 downto 0);

signal rst_n        : std_logic;
--signal start_stop   : std_logic;
signal start        : std_logic;
signal KEY_1_d1     : std_logic;
signal KEY_1_d2     : std_logic;

begin
--=======================================================
--  Structural coding
--=======================================================
LED <= i_led;
--PLL
pll_inst0: pll
port map (
          areset => not(KEY(0)),
		  inclk0 => CLOCK_50,
		  c0     => user_clk,      -- 2MHz
		  locked     => rst_n      -- reset di sistema
          );


-- LED

qsys_inst0: qsys_first_project
	port map (
		clk_clk              =>  CLOCK_50,
		reset_reset_n        => rst_n,
		pio_operation_export => operation_reg);

--start_gen_process: process(user_clk,rst_n)
--begin
--if rst_n = '0' then
--   KEY_1_d1 <= '0';
--   KEY_1_d2 <= '0';
--elsif rising_edge(user_clk) then
--   KEY_1_d1 <= KEY(1);
--   KEY_1_d2 <= KEY_1_d1;
--end if;
--end process start_gen_process;
--
--start_stop <= KEY_1_d2 and not(KEY_1_d1);

FSM_process: process(user_clk,rst_n)
begin
if rst_n = '0' then
   state <= s_IDLE;
   start <= '0';
elsif rising_edge(user_clk) then
   case state is
   when s_IDLE =>
      if operation_reg(0) = '1' then
	     state <= s_START_COUNT;
		 start <= '1';
	  else
         state <= s_IDLE;
         start <= '0';
      end if;
   when s_START_COUNT =>
	  if operation_reg(1) = '1' then
         state <= s_IDLE;
         start <= '0';
      else
	     state <= s_START_COUNT;
		 start <= '1';
      end if;
   end case;
end if;
end process FSM_process;

counter_process: Process(user_clk,rst_n)
begin
if rst_n = '0' then
   counter <= c_2MHz;
	i_led   <= "00000001";
elsif rising_edge(user_clk) then
   if start = '1' then
      if operation_reg(5 downto 2) = "0000" then 
   	     if counter = "000000000000000000000" then
   	         i_led <= i_led + 1;
             counter <= c_2MHz;
         else
             i_led <= i_led;
             counter <= counter - 1;
         end if;
      elsif operation_reg(5 downto 2) = "0001" then
   	     if counter = "000000000000000000000" then
   	         i_led <= i_led - 1;
             counter <= c_2MHz;
   	     else
   	         i_led <= i_led;
             counter <= counter - 1;
   	     end if;
      elsif operation_reg(5 downto 2) = "0010" then
   	     if counter = "000000000000000000000" then
   	         i_led <= i_led(0) & i_led(7 downto 1);
             counter <= c_2MHz;
   	     else
   	         i_led <= i_led;
             counter <= counter - 1;
   	     end if;
      elsif operation_reg(5 downto 2) = "0011" then
   	     if counter = "000000000000000000000" then
   	         i_led <= i_led(6 downto 0) & i_led(7);
             counter <= c_2MHz;
   	     else
   	         i_led <= i_led;
             counter <= counter - 1;
   	     end if;
      elsif operation_reg(5 downto 2) = "0100" then
   	     if counter = "000000000000000000000" then
   	         i_led <= i_led(6 downto 0) & i_led(7);
             counter <= c_2MHz_2;
   	     else
   	         i_led <= i_led;
             counter <= counter - 1;   
   	     end if;
      elsif operation_reg(5 downto 2) = "0101" then
   	     if counter = "000000000000000000000" then
   	         i_led <= i_led(6 downto 0) & i_led(7);
             counter <= c_2MHz_4;
   	     else
   	         i_led <= i_led;
             counter <= counter - 1;
   	     end if;
      elsif operation_reg(5 downto 2) = "0110" then
   	     if counter = "000000000000000000000" then
   	         i_led <= i_led(6 downto 0) & i_led(7);
             counter <= c_2MHz_8;
   	     else
   	         i_led <= i_led;
             counter <= counter - 1;
   	     end if;
	  end if;
   else
      counter <= c_2MHz;
	  i_led   <= i_led;
   end if;	
end if;
end process counter_process;

end struct;